1. Field of the Invention
The present invention relates to a display driver integrated circuit or IC (such as an LCD driver), a multi-bit driver IC (such as a printer driver IC), a multiple input/output IC (such as a sensor interface IC), a gate array, and the like. More particularly, the present invention relates to a semiconductor device in which circuit cells of the same circuit configuration and input or output electrodes are arrayed in pairs. Also, the invention relates to a data input/output device using such a semiconductor device.
2. Background of the Invention
The prior art common driver semiconductor integrated circuit for a liquid crystal display (LCD) is shown in FIG. 9 and comprises an N-bit shift register circuit portion 3 consisting of N stages, an N-bit latch circuit portion 5, an N-bit level shift circuit portion 6, and an N-bit driver circuit portion 7. A data signal input electrode i and a clock electrode 2 are connected with the shift register circuit portion 3. Data signals or display data signals DIN are applied to the shift register circuit portion 3 via the input electrode 1. Clock pulses CP are applied to the shift register circuit portion 3 via the clock electrode 2. The data signals DIN provided to the shift register circuit portion 3 via the input electrode 1 are transmitted from the first stage 31 to the final stage 3N serially every N clock pulses in synchronism with the clock pulses CP. The output QN appearing at the final stage 3N is supplied as output data signal DOUT to the next stage having a similar integrated circuit configuration via an external output electrode 4 for cascade connection.
The N-bit latch circuit portion 5 latches one row of data Q1, Q2, . . . , (QN) converted into a serial form by the shift register circuit portion 3. The level shift circuit portion 6 increases the output signals appearing at the individual stages of the latch circuit portion 5 from a logic voltage level of a low voltage of 3 to 5 volts to a higher voltage level for driving the LCD. The driver circuit portion 7 selects LCD driving power supply voltages V0, V2, V3, V5 in response to the outputs from the level shift circuit portion 6 in a 1:1 relation, shapes clock pulses M applied to an electrode 9 into AC driving waveform, and sends voltages Y1-YN to output electrodes 81-8N. In this integrated circuit, every stage has an identical in circuit configuration. The output electrodes, or pads, 81-8N correspond to the stages in a 1:1 relationship. Since the N-bit shift register circuit portion 3 and the N-bit latch circuit portion 5 are driven by the low voltage Vcc of the power supply voltage of 3 to 5 volts applied to an electrode 10, these stages a low voltage portion, L.V. On the other hand, a liquid crystal display requires liquid crystal driving voltages V0 (e.g., about 38 V), V2 (e.g., about 36 V), V3 (e.g., about 2 V), and V5 (e.g., about 0 V) be applied to the N-bit driver circuit portion 7 via electrodes 11, 12, 13, 14, respectively. Also, a high power supply voltage VH of about 40 V is applied to an electrode 15 which is connected with the level shift circuit portion 6 and also with the driver circuit portion 7. Therefore, the level shift circuit portion 6 and the driver circuit portion 7 form a high voltage portion, H.V.
Each one stage 3i of the shift register circuit portion 3, each one stage 5i of the latch circuit portion 5, each one stage 6i of the shift level circuit portion 6, and each one stage 7 of the driver circuit portion 7 together form a cell. Each cell, consisting of shift register 3i, latch circuit 5i and driver circuit 7i, and the corresponding output electrode 8i are referred to hereinafter as a pair. A general chip layout of such pairs is shown in FIG. 10, where all the stages are arranged in a parallel array forming semiconductor chip 18. In this figure, the zigzag portions indicated by the solid lines indicate the positions at which conductive leads intersect with each other. As a whole, the cells and the electrodes are arranged symmetrically with respect to the central line of the chip extending in the X-direction. Specifically, the chip cell array is divided into a first block 16 and a second block 17. The stages 31-3N of the shift register circuit portion are formed in the center of the chip. The stages 71-7N of the driver circuit portion are formed on the outer fringe of the chip 18, or along the longer sides. The output electrodes 81-8N are arranged on the outer side of the stages 71-7N of the driver portion on the outer fringe of the chip. A conductive lead for a high voltage VH and conductive leads for liquid crystal driving power supply voltages V0, V2, V3, V5 extend from the pads across the first block 16 on the driver circuit portion 7 and on the level shift circuit portion 6 in the X-direction, extend in the direction opposite to the Y-direction, and then extend across the second block 17 in the direction opposite to the X-direction. A conductive lead for the low power supply voltage Vcc extends from the corresponding pad across the first block 16 on the latch circuit portion 5 and on the shift register circuit portion 3 in the X-direction, extends in the direction opposite to the Y-direction, and extends across the second block 17 in the direction opposite to the X-direction.
The chip 18 of the LCD driving semiconductor integrated circuit of this layout is installed, for example, on a tape carrier or film by TAB (tape automated bonding). As shown in FIG. 11, the chip 18 can be directly installed on a liquid crystal panel. This is known as COG (chip on glass) techniques. In particular, the liquid crystal panel comprises a lower glass substrate G1, an upper glass substrate G2, a spacer 19 that maintains a spacing between the two substrates, and a liquid-crystalline material LC which occupies the space between the two glass substrates. Transparent row electrodes 20 and transparent column electrodes 21 are formed on the substrate. As shown in FIG. 11B, the chip 18 is directly bonded to the flat surface of a marginal region 22 of the glass substrate which forms a non-display region by the COG techniques. Bumps 24 are deposited on the electrodes, or pads, of the chip 18. The bumps 24 are bonded to the transparent row electrodes 20 or to the transparent column electrodes 21, for example, by thermocompression bonding or solder bonding to effect outer lead bonding. Conductive leads 23 extending to the fringe of the marginal region 22 form terminals for connection with a printed-wiring board (not shown).
In the chip 18, whose power supply leads are configured as described above, the leads for the power supply, voltages VH, V0, V2, V3, V5, Vcc and a lead for grounding (GND) extend from the electrodes, or pads, formed in the marginal region of the chip, draw a U-shaped configuration or an open loop, as shown in FIG. 10, and terminate at the final stages 3N, 5N, 6N, 7N of the second block. The voltages at the final stages of the second block tend to vary or be different from those voltages applied to the vicinities of the pads. This is due to the increased the lead lengths which translate to increased impedances of leads when approaching the final stages. In such a case, the lengths of the leads for the liquid crystal power supply, for example, are in excess of 10 mm. Even if the conductive leads are made of a metal, their resistance are generally tens of ohms. Fluctuations or variations in the power supply voltage applied to the final stages, as compared to the earlier stages, tend to cause a nonuniformity of the contrast of the liquid crystal display. Although it is possible to connect the leads at the final stages with the leads at the first stages so as to form a full loop without interrupting the power supply leads at the final stages by the multilayer interconnection techniques, the points at which the power supply leads intersect with each other and the points at which the power supply leads cross the signal leads increase in number. In such configurations, fabrication is more difficult and the quality of such circuits is degraded. Thus, it is inevitable that the impedance varies among the leads. As a result, the output characteristic of the driver circuit portion differs from display bit to display bit. Indeed, the leads can be made to form a loop, but the area occupied by the leads increases. Increasing the chip size increases the width W of the marginal region 22 in which the chip 18 is bonded as shown in FIG. 11. The liquid crystal display is preferred to have width W of the marginal region 22, comprising a non-display region, reduced to a minimum. In recent years, the liquid crystal display has tended to have increasingly finer picture elements. With this trend, the chip 18 has more and more display bits. Under these circumstances, the width W is required to be increased to accommodate more leads. Hence, the area occupied by the leads must be suppressed further to reduce the size of the display.
It is an object of this invention to provide a semiconductor device which comprises circuit cells and input or output electrodes arrayed in pairs, and has improved chip layout for suppressing variations in electrical lead impedance without increasing the space occupied by the leads, thereby making the input or output characteristic of the circuit cells and the corresponding display bits uniform. It is another object of the invention to provide a data input/output device having a narrower margin region on which a chip is installed.
In accordance with first aspect of this invention, a semiconductor device such as an IC for driving an LCD comprises an array of cells having substantially the same circuit configuration. In this type of semiconductor device, an electrode is provided for each cell for external electrical connection. In accordance with this aspect of the invention, the rows of the electrodes are formed on the inner side of marginal regions of a semiconductor chip, and that a circuit cell array is formed in the non-marginal regions located between the rows of the electrodes and the marginal regions of the semiconductor chip. The circuit cell array, forming the main portion of the chip circuitry, are not formed in the marginal regions of the semiconductor chip like in the prior art techniques. In this layout, i.e., the rows of the electrodes are disposed in the central region of the chip so that the chip can be fabricated to have a narrower width than previously possible. Also, when the leads are installed and bonded to the electrodes, short circuiting at the edge of the chip can be prevented Where the semiconductor chip is bonded by TAB, it is desired to connect the inner leads to the chip electrodes from a remote side of the chip, which are substantially parallel to the rows of the electrodes, to increase the lengths of the portions of the inner leads that over lie the chip. When the chip is bonded to a substrate of the device, outer leads are connected from the inner leads via extended lead portions with electrodes formed on the substrate. The presence of the overlying portions can reduce the dense region or the occupied width on the substrate.
In accordance with second aspect of the present invention, a semiconductor device has a circuit cell array divided into two or more blocks, the electrodes for the cells are divided into a first electrode row belonging to the first block and a second electrode row belonging to the second block. In accordance with this invention, the circuit cell array of the first block is formed in a first non-marginal region between a first longer side of the semiconductor chip and a first electrode row formed in a central region of the chip. The second circuit cell array of the second block is formed in a second non-marginal region between the second longer side, opposite to the first longer side, and the second electrode row formed in the central region of the chip. This layout of the semiconductor device permits the lengths of portions of the inner leads, which overlie the chip, to be increased. As a result of this construction, the above mentioned advantages can be achieved. Preferably, both rows of electrodes are disposed adjacently to each other, but it is not always necessary that both rows be neatly aligned. As an example, where both rows of electrodes are arranged in a zigzag fashion, the chip width can be reduced. Also, the width of the surface to which the chip is bonded can be decreased. Preferably, power supply electrodes and a grounding electrode are formed adjacent to, and on the outer ends of or at one end of the longitudinal extent of the electrode rows in the central region of the circuit cell array. In the chip having the electrodes arranged in lines in this manner, conductive leads for the power supply electrodes and the grounding electrode are arranged forming concentric, closed loop lead lines, i.e., circular-shaped connections are made. Reductions in the lengths of the leads and a reduction in the number of the intersections of the leads can be simultaneously attained. Consequently, the input or output characteristics can be made substantially more consistent among display bits so that there is less difference in contrast among the display bits. Furthermore, where a row of input/output electrodes for making external electrical connections is formed along one shorter side of the semiconductor chip adjacent to the power supply electrodes and the grounding electrode, all the electrodes form a substantially I-shaped arrangement. When the chip is directly installed via TAB, the inner lead ends of the lead pattern are automatically made parallel to the chip electrodes leads pads due to this I-shaped arrangement. Where the chip electrodes are connected with the inner leads, it is desired that each inner lead be either supported at both ends to the electrodes for the circuit cells or suspended at both ends from these electrodes. The straight arrangement of the electrodes makes it easy to arrange the chip parallel when batch bonding is performed. In accordance with this aspect of the present invention, a decrease in the stress can also be expected. This improves the alignment which, in turn, enhances the yield of batch bonding. The surface of the chip is coated and protected by the inner leads and, therefore, the active surface of the chip is prevented from being damaged and scratched during the bonding process. As a result of such construction, the heat-dissipating characteristics are improved. By mounting the chip having the leads, as described above, on a substrate of a LCD panel by the method described above, the width of the driver chip region on the marginal edge of the substrate can be reduced and the LCD panel can be made of more compact size.